January 2007 - BRION, TOOL CORP. UNVEIL INTEGRATED IC DESIGN ENVIRONMENT

TOOL's layout visualization platform, LAVIS, combined with Brion's computational lithography system, Tachyon, addresses all stages in design for manufacturing flow

TOKYO, Japan, January 18, 2007 — TOOL Corp. and U.S.-based Brion Technologies Inc. today announced the successful development of an integrated IC design environment that incorporates both TOOL’s versatile layout visualization platform, LAVIS, and Brion’s highly accurate and ultra-fast OPC and RET/OPC verification system, Tachyon.

This integrated environment is an essential tool for semiconductor fabs, photomask shops and fabless IC design houses that pursue design for manufacturing (DFM) solutions now and in the future. TOOL and Brion have combined LAVIS' large-volume data handling and high-speed data display capabilities, which can utilize all the data formats used throughout the chip design processes, with Tachyon, a manufacturing-proven computational lithography platform that is able to execute high-speed, full chip simulation and inspection with high precision.

This integrated environment can first display chip design data with LAVIS, conduct lithography simulation of designated areas of that design within Tachyon, and then display the results again with LAVIS. Because design data and simulation parameters are seamlessly and automatically communicated between LAVIS and Tachyon, the user is able to easily obtain simulation results without difficult and complex data preparation.

"TOOL and Brion's integrated design environment is most welcome," said Hiroshi Sakuma, general manager of NEC Electronics Corp.’s Technology Foundation Development Operations Unit, Design Engineering Division. "Hot spots are already becoming an issue with leading edge IC designs, and these problems will only increase with future technology nodes. The ability to perform Tachyon’s high precision lithography simulation easily and repeatedly through LAVIS’ design environment is critical to solving problematic hot spots."

As chip geometry continues to shrink from 65nm designs to 45nm and then 32nm, device patterns are becoming more complex because of the optical proximity correction (OPC) used to ensure that sub-wavelength features in these patterns are transferred correctly onto silicon. To achieve accurate OPC, it is critically important for high-speed, accurate simulation to verify design data and OPC data during the design process, which is provided by Brion's Tachyon.

But the complex, aggressive OPC patterns being incorporated into today's leading-edge designs can result in skyrocketing increases in the data volumes of these designs. In the past this has made data handling extremely difficult and time consuming. However the integration of TOOL and Brion's platforms together enables repeated high speed simulations and verifications to address hot spots and parameter alterations, as well as data modifications, thanks to LAVIS’ partial editing capability, bringing about substantial improvement of design verification turn-around time.

"It is certainly a pleasure to be able to provide our customers with a powerful DFM solution that incorporates Tachyon as well as TOOL's excellent layout platform, LAVIS," said Shauh-Teh Juang, Brion's senior vice president of marketing and business development. "We intend to further strengthen our collaborative effort with TOOL and LAVIS to continue to bring the best design and computational lithography solutions to our mutual customers."

"We are very excited to enhance the value of our versatile layout visualization platform LAVIS through its integration with Brion's award-winning high-performance, high-precision lithography simulation engine, Tachyon," said Hideaki Hontao, president of TOOL. "United together, we can tackle the design and manufacturing issues facing the chip industry today and tomorrow, as we continue our borderless and global collaboration."

The integrated LAVIS/Tachyon environment will be exhibited at the EDSFair this month in Yokohama, Japan.

About Tachyon

Tachyon is a hybrid computational lithography system used to perform OPC and verify RET/OPC through full chip simulation utilizing a combination of image-based lithography processing and polygon-based data processing.

About LAVIS

LAVIS is a versatile and ultra-high speed layout visualization platform that supports large data and multiple file formats. Its unique display method, coupled with memory management control technology, efficiently enables large volume data handling and fast display. Most importantly, LAVIS can be used as the common standard layout platform for all the IC processes such as design, verification, mask data preparation, inspection and failure analysis, thanks to its capability to support various data formats, including the GDSII design format and e-beam formats thereby making it easy to interface with other tools for the entire IC making flow.

About Brion Technologies

Brion Technologies is the worldwide leader in computational lithography for integrated circuit Lithography-Driven Design and Manufacturing(tm). Brion's Tachyon(tm) platform, a highly accurate and ultra-fast OPC and RET/OPC verification system, enables a unique set of capabilities that address the interrelated challenges of design, photomask making and wafer printing for semiconductor manufacturing. Headquartered in Santa Clara, CA, Brion leads the worldwide market for optical proximity correction (OPC) verification, and is rapidly expanding in the OPC market. For further information, visit www.brion.com or call +1 (408) 653-1500.

About Brion Technologies K.K.

Brion K.K. was founded in Tokyo in November 2005 to offer greater support to Brion’s design-for-manufacturing (DFM) customers in Japan. The company considers Japan to be one of the world’s most important regions for semiconductor manufacturing technology development, especially in the areas of device design, R&D, photomask production and lithography exposure tool manufacturing.

Lithography-Driven Design & Manufacturing and Tachyon are trademarks of Brion Technologies, Inc.

About TOOL

TOOL is a Japanese software development company focused primarily on EDA tool development. Its particular strength is in the area of layout design, and has scored a number of achievements in this area with its development tool, LAVIS. Solutions to chipmakers' problems can be provided by combining TOOL’s package-software with its custom-tailored software developed to serve a customer’s particular need. TOOL provides ample experience in this particular area. For more information on TOOL and products, Please refer to http://www.tool-corp.com.

Contact:

Brion Technologies, Inc
Reeka Ninomiya
Corporate Communications Manager
+1(408)200-0842
rninomiya@brion.com

Brion Technologies K.K.
Noriaki Kikuchi
President, Japan Operations
+ (81) 3-5298-1561
nkikuchi@brion.com

Agency Contact:
Catherine Koo
Loomis Group
+1 (415) 489 7396
koo@loomisgroup.com

TOOL Corporation
Asako Nakane
Marketing Group
+ (81) 3-5723-8124
asako@tool.co.jp